1. Field of the Invention
The present invention relates to a non-volatile memory cell, and particularly to a three terminal memory element using a standard CMOS transistor.
2. Description of the Related Art
MOS (metal oxide semiconductor) transistors are well known in the art. An MOS transistor includes a source and a drain, formed as diffusion areas in the substrate, as well as a channel region extending between the source and drain. A gate, typically a polycrystalline silicon structure, is formed overlying the substrate. A gate oxide, formed with silicon dioxide layer, is provided between the gate and the channel region. A predetermined voltage on the gate creates the channel, which connects the source and drain. Thus, by controlling the voltage, an MOS device can be used as a switch having an ON or OFF state.
If the source and drain are N type formed in a P type substrate, then the MOS transistor is called an NMOS device. In a similar manner, if the source and drain are P type formed in a N type substrate, then the MOS transistor is called a PMOS device. A complementary metal oxide semiconductor (CMOS) integrated circuit includes both NMOS and PMOS transistors.
Static random access memory (SRAM) cells are well known, volatile memory cells fabricated using (CMOS) technology. Volatile memory cells lose their stored information when power is removed from the circuit. In this manner, SRAM cells can be easily reprogrammed to a different logic state. However, an unexpected loss of power requires reprogramming of the SRAM cells.
In contrast, non-volatile memory cells preserve their stored information even if power is removed. Moreover, many applications for integrated circuits require the security provided by non-volatile memory cells. Therefore, it would be desirable for integrated circuits to include both non-volatile and volatile memory cells, thereby providing the end user with optimal flexibility as well as security.
However, conventional, non-volatile memory cells are substantially different from those used in typical, volatile memory cells, thereby requiring different fabrication techniques. Thus, if non-volatile memory cells are included on an integrated circuit fabricated using conventional CMOS technology, then chip size and complexity are undesirably increased.
FIG. 1A illustrates a known memory system 100 located on an integrated circuit with other circuitry (not shown). This circuitry can include, for example, circuitry relating to a field programmable gate array (FPGA). In one embodiment, memory system 100, which includes both low voltage and high voltage transistors, is fabricated in accordance with a 0.18 .mu.m CMOS process. The low voltage transistors are designed to operate in response to a supply voltage of 1.8 Volts, whereas the high voltage transistors are designed to operate in response to a supply voltage of 3.3 Volts.
Memory system 100 includes an illustrative 4.times.4 array of memory cells 101, each memory cell 101 including a write access transistor 102, a storage transistor 103, and a read access transistor 104. Storage transistors 103 are low voltage NMOS transistors having a gate oxide thickness of 40 .ANG., a channel width of 0.6 .mu.m and a channel length of 0.25 .mu.m. Write access transistors 102 are high voltage PMOS transistors having a gate oxide thickness of 70 .ANG., a channel width of 1 .mu.m and a channel length of 0.6 .mu.m. In contrast, read access transistors 104 are high voltage NMOS transistors having a gate oxide thickness of 70 .ANG., a channel width of 10 .mu.m and a channel length of 0.6 .mu.m.
Storage transistor 103 is programmed by applying a programming voltage (VPP) across its gate oxide layer, thereby rupturing this layer. When the gate oxide is ruptured, a conductive path is formed between the gate, source, and drain of the storage transistor. If the gate oxide of a storage transistor is not ruptured, then no such conductive path exists. In the embodiment of FIG. 1, the drain and source of the storage transistor are connected to ground. Thus, to apply the programming voltage VPP across the gate oxide layer, a programming voltage VPP is applied to the gate of storage transistor 103.
The programming voltage VPP is applied to the gate of storage transistor 103 through write access transistor 102. However, the breakdown voltage of write access transistor 102 is at least 1.5 Volts higher than the breakdown voltage of read access transistor 104. In this manner, the high breakdown voltage of write access transistor 102 allows the use of a relatively high programming voltage VPP.
FIG. 1B illustrates the breakdown characteristics of a high voltage PMOS transistor (such as write access transistor 102), a low voltage NMOS transistor (such as storage transistor 103), and a high voltage NMOS (such as read access transistor 104). The breakdown characteristics of transistors 102, 103, and 104 are shown by lines 102A, 103A and 104A, respectively.
As illustrated by line 103A, the low voltage NMOS transistor has a breakdown voltage of about 6 Volts. However, as illustrated by line 104A, at 6 Volts, the high voltage NMOS transistor operates in a Fowler-Nordheim tunneling region, which may harm its gate oxide. (The Fowler-Nordheim tunneling region begins at the knee of the curve in line 104A.) Consequently, it is undesirable to use a high voltage NMOS transistor as a write access transistor.
As illustrated by line 102A, a high voltage PMOS transistor does not begin to operate in the Fowler-Nordheim tunneling region until about 7.5 to 8 Volts. Thus, there is a safe operating margin that exists between the breakdown voltage of a low voltage NMOS transistor (such as storage transistor 103), and the Fowler-Nordheim tunneling region of a high voltage PMOS transistor (such as write access transistor 102). This margin enables write access transistor 102 to safely transfer the programming voltage VPP.
Referring back to FIG. 1A, the memory cells in each row are coupled to a common write word line (WWL) and a common read word line (RWL). Similarly, the memory cells in each column are coupled to the common read bit line (RBL) and a common write bit line (WBL). Word line control circuit 120 generates the read and write enable signals to be applied to read word lines RWL and write word lines WWL, respectively. Bit line control circuit 130 generates the program signals to be applied to write bit lines WBL and the read enable signals REN. Detailed descriptions of word line control circuit 120 and bit line control circuit 130 are provided in U.S. patent application, Ser. No. 09/263,375, filed on Mar. 5, 1999, which is incorporated by reference herein.
Write Operation
To program a specific memory cell 101, word line control circuit 120 asserts a supply voltage VCC on the write word line WWL of the addressed row. Bit line control circuit 130 then asserts the programming voltage VPP on the write bit line (WBL) of the addressed column. Under these conditions, write access transistor 102 turns on, thereby applying the programming voltage VPP to the gate of storage transistor 103. Under these conditions, the gate oxide of storage transistor 103 is ruptured, thereby programming that memory cell.
Word line control circuit 120 further applies the VCC supply voltage to all read word lines RWL. Thus, the gate-to-drain voltage of read access transistor 104 in the programmed memory cell is limited to a voltage that does not exceed the programming voltage VPP minus the VCC supply voltage. Note that this voltage is only applied until the programming operation is complete (i.e., the gate oxide is ruptured). At this time, the gate-to-drain voltage is approximately VCC. Consequently, the gate oxide of read access transistor 104 in the programmed cell is not damaged during a programming operation.
Bit line control circuit 130 provides the VCC supply voltage to all of the write bit lines WBL in the non-addressed columns. As a result, except for the addressed memory cell, the gates and sources of write access transistors 102 in the addressed row are held at the same voltage (i.e. VCC). Consequently, those transistors are turned off, and the associated storage transistors 103 are not programmed.
Word line control circuit 120 further provides the programming voltage VPP on the write word lines WWL of the non-addressed rows. As a result, except for the addressed memory cell, the gates and the sources of the write access transistors 102 in the addressed column are held at the same voltage (VPP). Consequently, those transistors remain turned off, and the associated storage transistors 103 are not programmed.
Note that the gates of write access transistors 102 in the non-addressed rows and columns are held at the programming voltage of VPP, whereas the sources of these transistors are held at the VCC supply voltage. Because the gate voltages are greater than the source voltages, these transistors are turned off and the associated storage transistors 103 are not programmed.
Bit line control circuit 130 further provides read enable signals REN having a voltage of 0 Volts during a program operation. Consequently, read output transistors 141 are not turned on during a programming operation. Therefore, read bit lines RBL are left floating.
Table 1 summarizes the various voltages applied to the addressed and non-addressed rows and columns during a write operation.
TABLE 1 Non- Non- Addressed Addressed Addressed Addressed Row Row Column Column WWL 1.8 V 8 V -- -- RWL 1.8 V 1.8 V -- -- WBL -- -- 8 V 1.8 V REN -- -- 0 V 0 V RBL -- -- Float Float
Read Operation
During a read operation, word line control circuit 120 provides the VCC supply voltage to all write word lines WWL, and bit line control circuit 130 provides 0 Volts to all write bit lines WBL, thereby turning off all write access transistors 102. The gate of pull-up transistor 143 is coupled to ground, thereby turning on that transistor and weakly pulling up the voltages on the drains of transistors 141 to the VCC supply voltage. To read the state of a specific memory cell 101, bit line control circuit 130 asserts the VCC supply voltage on the read enable line REN associated with the addressed column. Under these conditions, read output transistor 141 in the addressed column turns on, thereby coupling the associated read bit line RBL to the drain of pull-up transistor 143.
Bit line control circuit 130 provides 0 Volts on read enable lines REN associated with non-addressed columns. Consequently, transistors 141 in the non-addressed columns are turned off, thereby leaving their associated read bit lines RBL floating.
Word line control circuit 120 provides 0 Volts to all of the row word lines RWL in the non-addressed rows. Therefore, read access transistors 104 in the non-addressed rows are turned off, thereby preventing the associated memory cells 103 from being read.
To read the addressed memory cell 101, word line control circuit 120 asserts the supply voltage VCC on the read word line RWL of the addressed row. Under these conditions, read access transistor 104 turns on, thereby coupling the gate of storage transistor 103 to read bit line RBL.
If storage transistor 103 is programmed, a conductive path will exist through storage transistor 103. Under these conditions, storage transistor 201 will overcome the weak pull up provided by pull-up transistor 143 and pull down the voltage on read bit line RBL to approximately 0 Volts. As a result, memory system 100 provides a logic low output signal OUT.
Conversely, if storage transistor 103 is not programmed, no conductive path exists through storage transistor 103. Under these conditions, with no active pull down, pull-up transistor 143 pulls up the voltage of read bit line RBL to approximately VCC. Therefore, memory system 100 provides a logic high output signal OUT.
Table 2 summarizes the various voltages applied to the addressed and non-addressed rows and columns during a read operation.
TABLE 2 Non- Non- Addressed Addressed Addressed Addressed Row Row Column Column WWL 1.8 V 1.8 V -- -- RWL 1.8 V 0 V -- -- WBL -- -- 0 V 0 V REN -- -- VCC 0 V RBL -- -- Coupled Float to Output Line
Under certain conditions, a programmed storage transistor 103 may begin to self-repair. Specifically, during programming the gate oxide is ruptured, thereby allowing some of the material associated with the gate of the storage transistor to collapse into the area overlying the channel region of the storage transistor. In this manner, some portion of the gate is fused with the source and drain of the storage transistor. The original ON state resistance of the cell depends on the programming current. In the embodiment described above, an ON state resistance of 10-50 kOhms is typical.
However, if the memory cell is repeatedly read, the fuse begins to deteriorate, thereby increasing the ON state resistance of the cell. In time, the fuse may deteriorate completely, thereby separating the gate from either the source or the drain regions. At this point, a programmed memory cell in the embodiment of FIG. 1 actually reads as an unprogrammed memory cell and cannot be reprogrammed.
Therefore, a need arises for a reliable, non-volatile memory cell formed using standard CMOS processes.